Search results for "Application-specific integrated circuit"
showing 10 items of 18 documents
Electrical Modeling of Monolithically Integrated GMR Based Current Sensors
2018
We report on the electrical compact model, using Verilog-A, of a monolithically integrated giant magnetoresistance (GMR) based electrical current sensors. For this purpose, a specifically designed ASIC (AMS $0.35\mu \mathrm{m}$ technology) has been considered, onto which such sensors have been patterned and fabricated, following a two-steps procedure. This work is focused on the DC regime model extraction, giving evidences of its good performance and stating the bases for subsequent model improvements.
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
Analysis and Visualization of Product Memory Layout in IP-XACT
2017
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW also for the SW needs. The HW design connectivity and overall memory layout may change due to component instantiations, configurations and conditional operation states, which makes it difficult to create register tables even for documentation. Current register design tools fall short in serving th…
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC
2015
[EN] The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the tota…
Monolithic integration of GMR sensors for standard CMOS-IC current sensing
2017
Abstract In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a de…
A high resolution TDC subsystem
1994
A high resolution TDC subsystem was developed at the Institute for Nuclear Physics in Mainz. The TDC chip offers a time resolution of less than 300 ps and a programmable measurement range from O to 16 /spl mu/sec. The time measurement is done with a new, purely digital counting method. The chip can be operated in common start or common stop mode. In common start mode the chip is able to store up to 4 multiple hits per channel. The chip is used to build a transputer controlled subsystem for the measurement of the drift times of a vertical drift chamber. The design of the subsystem will be described and the first results from the tests of the prototype system will be presented. >
Performance of the front-end electronics of the ANTARES neutrino telescope
2010
ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named Analogue Ring Samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the fu…
Detector characterization and first coincidence tests of a Compton telescope based on LaBr3 crystals and SiPMs
2011
International audience; A Compton telescope for dose monitoring in hadron therapy consisting of several layers of continuous LaBr3 crystals coupled to silicon photomultiplier (SiPM) arrays is under development within the ENVISION project. In order to test the possibility of employing such detectors for the telescope, a detector head consisting of a continuous 16 mm×18 mm×5 mm LaBr3 crystal coupled to a SiPM array has been assembled and characterized, employing the SPIROC1 ASIC as readout electronics. The best energy resolution obtained at 511 keV is 6.5% FWHM and the timing resolution is 3.1 ns FWHM. A position determination method for continuous crystals is being tested, with promising res…
An integrated calibration system for liquid argon calorimetry
1999
Abstract A novel technical solution for an integrated version of the pulse generator of a calibration system for liquid argon calorimeters is presented. It consists of a differential amplifier with automatic offset compensation, a current mirror and a switching logic. These components are integrated on an ASIC chip in CMOS technology. The technical realisation as well as results on the performance are presented.
Position sensitive scintillator based detector improvements by means of an integrated front-end
2009
PESIC is an integrated front-end for multianode photomultiplier based nuclear imaging devices. Its architecture has been designed to improve position sensitive detectors behavior by equalizing its response over its whole area. Its preamplying stage introduces two main benefits: digitally programmable gain adjustment for every photomultiplier output, and isolation from other front-end electronics by means of current buffers. This last feature allows to use different types of photomultipliers and optimizes front-end deadtime, reducing impact position dependent output delay. PESIC also includes an indirect measurement of the depth of interaction of the gamma ray inside the scintillator crystal…